Page 23 - PCB-West-2020-Catalog

TECHNICAL CONFERENCE PROGRAM
5: Semi-Additive PCB Processing Resets the Technology Curve
Mike Vinson, Averatek, and Kelly Dack, KeyTronic
The continued miniaturization of both packaging and component size in next-generation electronics presents a challenge for PCB designers to effectively navigate the constraints of the traditional subtractive etch PCB fabrication processes and contribute to the need for finer feature size, higher layer count, stacked microvias and increased lamination cycles. Semi-Additive PCB processes provide an alternative that effectively resets the technology curve while increasing reliability.
The ability to design with and manufacture a 25-micron trace and space repeatedly and reliably provides options and opportunities previously not available to PCB designers. While just scratching the surface, the ability to reduce the number of layers needed for routing high-density BGAs, increase hole size, reduce the number of micro via layers required, dramatically reduce size, weight and packaging and conversely increase the electronic content within an existing footprint are benefits being explored and realized as these feature sizes are being applied to new PCB designs.
This session will explain the science and technology behind the semi-additive process and how this process is currently being integrated with traditional subtractive etch chemistries and equipment. As with any emerging technology, there are many questions. The session will continue by addressing frequently asked questions from both a fabrication and design perspective. Once the fundamentals of the process are understood, the session will continue with use cases showing various ways that this technology can be applied to PCB designs. Examples provided will include a starting point with traditional design rules, highlight various ways that a 25-micron trace and space capability could be applied and demonstrate resulting benefits to layer count, size and overall complexity.
Time will be allocated for specific questions and overall industry discussion around semi-additive processes, how they integrate with subtractive etch processing and potential benefits.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator Target audience: Beginner, Intermediate, Advanced
6: Causes of Signal Degradation in PCB Transmission Lines
Atar Mittal, Sierra Circuits
Signal degradation on PCB transmission lines manifests in many forms: undershoot, overshoot, ringing, pulse shape distortion, switching noise, attenuation, ground bounce, skew, etc. All these can be attributed to one or more of these sources: signal reflections caused by characteristic impedance discontinuities; signal distortion due to conductor and dielectric losses resulting from PCB materials’ properties as signals travel over the transmission lines; crosstalk from signals on nearby PCB conductors; noise in power distribution network; electromagnetic interference (EMI). Impedance discontinuities manifest from many sources, to name a few: unmatched loads and terminations, non-uniformity in the lines, vias, stubs, component and test pads, gaps in reference planes and poorly designed return paths, stray capacitances and inductances, and branching of signal paths, and all these cause signal reflections. Frequency dependence of the copper and dielectric losses cause unequal attenuation of various frequency contents in the signals, causing signal rise time degradation, and variations in dielectric constant with frequency cause different frequency signal components traveling at different speeds.
Crosstalk from nearby conductors occurs due to inductive and capacitive coupling, causing several issues: near- and far-end crosstalk, switching noise, ground bounce, etc. PDN noise and unwanted electromagnetic energy will superimpose on signals causing signal integrity issues. After identifying the root cause, one can find solutions to the signal integrity problem.
Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer Target audience: Intermediate
12:00 pm – 1:00 pm
LUNCH and LEARN, Sponsored by Summit Interconnect
1:00 pm – 3:00 pm
7: From Smart Factory Automation to Digital Twin Standard: Ushering a New Era for Design and Manufacturing
Michael Ford, Aegis Software, and Hemant Shah, Cadence
The new IPC Digital Twin standard (IPC-2551) defines an interoperable framework in which thousands of applications from multiple sources work seamlessly together, providing the opportunity for virtual prototyping of all aspects of design, manufacturing and beyond. Use of IPC-2551 prevents companies in all areas of the industry from making the mistake of tying themselves to any monopolistic data exchange technology. The impact of the IPC Digital Twin on the design through manufacturing flow will be significant, and will be the area that develops sooner than any other, built upon and driven by existing IPC standards, such as IPC-2581 (DPMX), IPC-2591 (CfX) and IPC-1782 internal and external (secure supply-chain) traceability. This presentation explains the IPC Digital Twin standard, using some specific use-case examples that illustrate the value and opportunity that the standard provides to both the design and manufacturing communities, exchanging digital models bidirectionally between design and manufacturing. This presentation will be of critical interest to all of those involved in design and manufacturing, including business management, engineers and technology providers.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
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