Page 29 - PCB-West-2020-Catalog

TECHNICAL CONFERENCE PROGRAM
manner as a problem-solving approach. Silicon vendor support documents (e.g., constraint and spreadsheet tools) to address power integrity are introduced and briefly discussed. Examples from various industries (e.g., automotive, industry automation, IoT) will complement the session with practical application experience.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer Target audience: Beginner, Intermediate, Advanced
12:00 pm – 1:00 pm
LUNCH ON SHOW FLOOR, Sponsored by Sierra Circuits
1:30 pm – 3:30 pm
16: Novel Power Distribution System Design
Daniel Beeker, NXP Semiconductor
This presentation will present a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC. New research is presented on the impact of discrete components on radiated and conducted emissions, with an emphasis on cost analysis. This course will, after an introduction to EM field behavior, describe several effective methods for designing the spaces used to deliver power on a PCB. These methods are driven by considerations for how fast the switches are changing states and the geometry of the spaces and placement of components to properly deliver energy to prevent EMC and signal integrity issues.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer Target audience: Beginner, Intermediate, Advanced
1:30 pm – 5:00 pm
17: Circuit Grounding to Control Noise and EMI
Rick Hartley, RHartley Enterprises
When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent. This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for I/O connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer Target audience: Intermediate
18: PCB Design and Assembly Process Strategy for High Density CSP, WLP, 2D and 3D Semiconductor Package Technology
Vern Solberg, Solberg Technical Consulting
Topics covered: 1. BGA/CSP process technologies and standards; single die BGA and FBGA packaging, flip-chip and die-size package technologies, wafer level packaging (WLP), fan-out wafer-level packaging (FOWLP), JEDEC package outline standards. 2. Innovative solutions for 2D, 2.5D and 3D packaging, 2D BGA package technology, 3D multiple die and stacked package methodologies, implementing 2.5D for high-density BGA applications, silicon-based interposer structure, glass-based interposer structures, organic (laminate) based interposer structures. 3. Printed circuit board design guidelines for HDI, ball grid array (BGA), fine-pitch ball grid array (FBGA and DSBGA), flip-chip (WLP/FOWLP), 2.5D interposer structures; 4. HDI circuit and microvia design implementation, HDI circuit fabrication variations, microvia process methodology, design guidelines for HDI circuits, HDI sources and economic issues. 5. Specifying PCB base material, surface finish and coatings, organic-based material selection criteria, specifying thickness of copper foils, surface plating and coating variations, solder mask process considerations; 6. Preparation for high-volume assembly processing, surface mount assembly process overview, basic features needed for SMT assembly processing, system requirements for BGA and CSP device placement, palletizing to maximize assembly process efficiency, assembly process implementation.
Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator Target audience: Beginner, Intermediate, Advanced
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