Page 31 - PCB-West-2020-Catalog
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 TECHNICAL CONFERENCE PROGRAM
 19: Designing the Signal Return Path
Susy Webb, Design Science
When designing a PCB, the signal routing and its return are critical to the circuit working properly. Great care is usually given to routing the signals, but often the return portion is the last thing considered, or sometimes it is forgotten altogether. This presentation will talk about the importance of designing that return path, with a discussion of the physics involved, where the energy flows, the interference caused when it is not controlled, and the planes and stackup needed. Additionally, we will discuss the best ways to contain energy fields, the spacing that helps prevent problems, and the routing and return movement from layer to layer. Throughout, we will discuss some signal routes and look at the paths that might set up the best possibility for a clean return.
Who should attend: PCB Designer/Design Engineer Target audience: Intermediate
20: The PCB Design Process from Cradle to Grave
Daniel J. Smith, Raytheon SAS
This half-day course is an overview (past, present, and future) of the interactions of processes, people and technologies involved in the complete lifecycle of a PCB design. This course is designed to provide a solid foundation for those who are just starting out (zero to two years of experience) as a PCB designer and help the individual formulate a roadmap to build their knowledge base for both personal and career advancement as contributors to this industry.
All attendees will receive an MS Excel checklist of the traditional questions that PCB designers should ask throughout the PCB design process.
Who should attend: PCB Designer/Design Engineer Target audience: Beginner, Intermediate
21: Place and Route for Dense High-Speed and RF Circuits
Michael R. Creeden, CID+, Insulectro
This presentation will offer a complete view of place-and-route for dense high-speed and RF circuits. We will cover a wide range of topics, including next- generation materials, the rationale for considering HDI for our products, and overall layout flow. We will discuss the technological challenges we face in both the schematic circuit rules capture, design layout and manufacturing process. Students will learn what it takes to satisfy solvability, high-speed concerns, and RF performance issues, while building a board that will be cost-effective as a reliable high-yield product. We will also review how our early integration with the manufacturing team during the design cycle will help us understand the specifics to build a product that is correct-by-construction and performs on revision-1. The focus will be on practical application and implementation using real-world examples.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer Target audience: Beginner, Intermediate, Advanced
3:00 pm – 5:00 pm
22: The Mystery of Bypass Capacitors
Keven Coates, Geospace Technologies
How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer Target audience: Beginner, Intermediate, Advanced
5:00 pm – 6:00 pm
HAPPY HOUR ON SHOW FLOOR - Free networking reception on the show floor Free Wednesday
9:00 am – 10:00 am
F1: The Butterfly Effect in PCB Design: Optimization of High-speed Lines for an FMC Carrier Board
Jamie Pacamarra, Analog Devices
When signals start to get affected by the physical characteristics of the PCB, things start to get a little tricky. A simple point-to-point connection won’t be enough to keep the integrity of the signal. High-speed PCB design focuses on addressing this issue by altering the physical conditions of and around the traces concerned.
This study is focused on an FPGA mezzanine card (FMC) carrier supporting the Software-Defined Radio (SDR) System-On-Module (SOM) from Analog Devices. It uses the peripheral component interconnect express (PCIE) topology that consists of both a transmitter pair and a receiver pair. These pairs send and receive
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