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 repetition of PDN consideration in SI-PI simulation. Worst-case single rank write and read margins were predicted with statistical simulation based on response surface methodology. The factors considered during simulations are PVT corners, impedance variation in package and PCB, SoC driver strength and ODT strength variation. Write and read eye diagram (including JEDEC eye mask) will be presented to affirm the claim.
Who should attend: PCB Designer/Design Engineer, System Designer, SI Engineer Target audience: Intermediate, Advanced
3:30 pm - 4:30 pm
F10: PCB Design as an Optimization Problem
Zachariah Peterson, Northwest Engineering Solutions
Causal transmission line design has been a critical aspect of behavior since the 100Gb/s Ethernet PHY guidelines were proposed by the IEEE P802.3bj Task Force. Causal effects in real transmission lines, as well as dispersion and losses in the system, cause deviations from target impedance, motivating a design technique that considers design to a target impedance throughout the relevant signal bandwidth. This talk presents the use of differential evolution for optimizing causal transmission line geometries to meet a target impedance while considering the entire bandwidth of an analog or digital signal (up to 20GHz). The transmission lines shown consider skin effect, causal relationships between dielectric function and losses, and copper roughness. The results show dielectric function at a single frequency is not always an appropriate approximation for calculating signal behavior on a transmission line. Example results for microstrips, striplines and coplanar waveguides will be presented. Differential evolution will be used to show tradeoffs between crosstalk strength and conformance to target impedance. This is done by taking multiple design goals as objective functions in optimization problems and designing the transmission line directly. This eliminates the need to take measurements of proposed interconnect designs and infer the required geometry from a regression technique. Results for single-ended and differential lines will be presented. These results provide designers a view of the tradeoffs involved in geometry and spacing optimization. These optimization techniques have never been used to directly address transmission line geometry within a defined bandwidth while considering the causal relations for the dielectric function of PCB substrates (e.g., Kramers-Kronig relations). These new techniques enable calculation of critical signal metrics in transmission lines, such as insertion loss, return loss, S-parameters, and crosstalk strength.
Who should attend: PCB Designer/Design Engineer Target audience: Advanced
5:00 pm – 6:00 pm
HAPPY HOUR ON SHOW FLOOR - Free networking reception on the show floor Thursday, Sept. 10
10:00 am – 6:00 pm
23: PCB Stackup Design and Materials Selection
Bill Hargin, Z-zero
The objective of this tutorial is to guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator Target audience: Beginner, Intermediate
10:00 am – 12:00 pm
24: Mechanical Design to Control EMI
Rick Hartley, RHartley Enterprises
Asmostengineersanddesignersareaware,EMIoccursbecausesomemechanicalstructure,withinorattachedtooursystem,iscapableofresonatingandradiatingelec- tromagneticfieldenergy.Thosemechanicalstructurescanbeacableattachedtothehousingaroundourcircuitboards,apartofthemetalchassis,aslotinthechassisora portionofoneofthecircuitboardsinthesystem.Knowinghowtocontrolthesestructuressotheyarenotcapableofsupportingresonanceandradiationisthekeytosuccess.
This two-hour course will discuss basic physics of energy movement, metal vs. plastic enclosures, slots and openings in enclosures, shielding enclosures, shield- ing of components, proper shielding of cables, basic component placement for MEs, extreme importance of I/O connector placement, routing of external cables, position of cables inside the system, multiple boards in the system — best arrangement, using chassis as a heatsink, other items MEs and PCB designers need to know about PCBs and the system.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer Target audience: Beginner, Intermediate

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