Page 39 - PCB-West-2020-Catalog
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 25: Design-for-Manufacture and Design-for-Assembly Fundamentals that Decrease Holds and Lower the Cost of Manufacturing
Mark J. Hughes, Royal Circuit Solutions, and Elijah Gracia, Royal Circuit Solutions
Engineers are often only peripherally aware of the PCB fabrication and assembly process, and often make design decisions that increase cost and turn-time or decrease reliability. This presentation provides a manufacturer’s perspective of design decisions that result in holds and cost increases using examples from the past 15 years in the industry. By gaining a better understanding of how manufacture and assembly processes work, engineers will be able to design printed circuit boards that cost less and have greater longevity than their current designs.
This presentation will be split into two parts: First, we will briefly cover all phases of the manufacturing process as we follow a board from digital submission to customer delivery. Second, we will look at multiple examples of actual customer submissions and analyze them for design decisions that result in unnecessary cost increases or unnecessary holds. The presentation will conclude with a 15-minute question and answer session that allows engineers to ask questions about their designs.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator Target audience: Beginner, Intermediate
26: How to Fight Magnetic Noise Gremlins
Keven Coates, Geospace Technologies
Have you ever had a noise-sensitive circuit and tried to find the noise source? Even after you completely encased sensitive portions in all sorts of shielding, you still had noise? It’s very possible this is magnetic noise. Lower frequency magnetic fields can’t be contained and shielded against in the same way electric fields can. In this presentation, hear about the author’s nine-month long battle with a specific magnetic noise issue, the best tools to fight it, twisted pair, current loops, and the best ways to test for and defeat magnetic noise in your designs. New this year is more on how electric fields compare and some general shielding examples.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer Target audience: Beginner, Intermediate, Advanced
27: PCB Design Techniques to Improve ESD Robustness
Daniel Beeker, NXP Semiconductor
Raise the shields, Scotty! Starting with some simple definitions for ESD/EOS, this session describes the important differences in the energy involved and the type of damage that can result. The presentation focuses on PCB design techniques as a means of improving system robustness.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer Target audience: Beginner, Intermediate, Advanced
10:00 am – 2:30 pm
28: Fundamentals of Geometric Dimensioning and Tolerancing (GD&T) for the PWB Designer
Gary Ferrari, FTG
Millions of dollars’ worth of PWBs are scrapped each year due to tolerance errors in the final product. A good majority of these errors are due to incorrect tolerancing of holes, edges and other board features. This seminar will explain how GD&T can help you avoid high scrap rates and reduce overall cost due to improper dimensional tolerances. It will show how to apply GD&T to printed wiring boards without all the confusion found in complex mechanical objects such as gear trains and castings. The principles discussed follow the ASME Y14.5 standard, as well as IPC-2615, Printed Board Dimensions and Tolerances. Attendees will learn GD&T principles for printed wiring boards, appropriate symbology for drawings, and bilateral vs. geometric dimensioning.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator Target audience: Beginner, Intermediate
12:00 pm to 1:00 pm
LUNCH AND LEARN, Sponsored by Polar Instruments
1:00 pm – 3:00 pm
29: Feeding the Beast: Consumption-Based PCB Design
Daniel Beeker, NXP Semiconductor
A step-by-step guideline for determining the PCB design requirements based on device energy consumption requirements. Wave cycle times and transmission line capacity form the basis of this philosophy. The course will center on the LS1043 network processor, with a focus on the core power supply requirements (7 A/μS). The session will begin with a review of EM field behavior and transmission line design, then will outline a process for analyzing the real power delivery challenge posed by a high-performance microprocessor. Starting with the DC current specification, we will use the device package pinout to determine the necessary PCB networks required to support the delivery of power to the device. The package pinout and clock frequency will be used to determine the real “coulombs per wave cycle” that the PDN must support. This will then be used to design both local storage requirements and connecting structures. A spreadsheet

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