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 multi-core CPU and cluster-based computing resources to evaluate multiple routing strategies at the same time. We have used the AI smart router to accelerate a variety of PCB designs from a special CPU interposer, power interposer to general open source PCBs, such as Raspberry Pi and Arduino boards, with great success. For example, the CPU interposer is a special kind of PCB used to enable previous generation silicon to be installed on a current generation system for validations before new silicon arrival. This facilitates platform checkout and deployment, enabling early shift left platform strategy, such as firmware, BIOS, and test and validation collateral developments. The routing time is reduced from three weeks of using manual routing to under one hour using the new AI router. The power interposer is analog-centric and used to profile silicon key power rail voltage and current, and the AI router can also achieve 100% completion rate in a very short time. The AI router works with a PI analysis tool to evaluate power rail shape changes on the PI performance to guarantee the design specification is met when routing changes are necessary. The router is web-based, so users can upload a board design database to the cloud. Once the routing is complete, users will be notified. Another benefit of the AI router is that it can greatly reduce design time, including pre-layout feasibility study, board stackup definition, and component placement. The course will provide a walk-through of the routing process using an AI router.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing Target audience: Beginner, Intermediate, Advanced
 2:30 pm – 3:30 pm
F7: Hair-Raising Footprint Horror Stories – and How to Avoid Them
Elizabeth Bustamante, SnapEDA
When creating libraries, standards are crucial for maintaining consistency, accuracy, and reliability. Yet, even with rigid standards in place, mistakes inevitably creep into such a detail-oriented process. In this talk, we’ll explore some hair-raising footprint horror stories and how to avoid fatal footprint mistakes on your next PCB design. Delving far beyond the basics, we’ll look at the more gnarly errors that trip up engineers. For example, we all know to double-check our pin mappings, but what about how you have interpreted the component’s orientation in the datasheet? Misinterpreting a component’s top view for its bottom view is one of the top causes of bad boards that we see.
Drawn from our community of 200,000 engineers, our hope is these lessons will prevent costly prototype iterations and delays on your next project. Finally, we’ll explore how to prevent these errors on your next designs. For example, by bringing in more verification into your processes through checklists or by creating an automated system for assessing the quality of your PCB footprints.
PCB Designer/Design Engineer, Hardware Engineer, Test Engineer Target audience: Beginner, Intermediate, Advanced
F8: The Current State of Fabrication and Assembly – Dispelling Myths, Correcting Misunderstandings, and Explaining Mysteries
Shane Shuffield, Advanced Assembly, and Mark Hughes, Advanced Assembly
Engineering is full of “rules-of-thumb” and “best-practices” based on false and outdated assumptions. Engineers need to know the current state of manufacturing technology to avoid unnecessarily constraining their design or basing their ERC and DRC on fictional rules.
This presentation will cover the current state of printed circuit board manufacturing and assembly technology, with an emphasis on correcting outdated rules and restrictions made obsolete by advances in machines, materials, and process control. Participants will gain insight into how certain design decisions can affect the cost and lead-time for their projects.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator Target audience: Beginner, Intermediate
 3:30 pm – 4:30 pm
F9: PSIJ Effect on SI Analysis of LP4x 4267 Mbps Speed in HHHL PCIe Card
Ashish Gupta, Intel and Vinay Kumar Naik, Intel
A system-level SI-PI co-simulation of LPDDR4x 4267 Mbps is presented. System analysis includes 1.6mm 14L PCB, 0.8mm 10L SoC flip-chip package with memory down configuration. The board stackup is 14 layers, 4-6-4 driven by high-density memory (4 - x64 slices) and HHHL (Half Height Half Length) form factor. The LP4x memory data bytes are routed in the upper half of the stackup with microvias on stripline layers to the crosstalk with zero via stub. The command, address and control signals are half-buried to ensure safe guidelines. The low Dk (<4) and Df (<0.1) material was chosen to minimize transmission and dielectric loss, respectively. Reverse-treated foil (RTF) is used, which offers significant improvement in loss characteristics at high-speed data transfer. The FCBGA package contains approximately ~10K bums and ~2K BGA pads with 4-2-4 stackup. Die form-factor is 14 x 16mm2, to keep the package form factor as low as 25 x 25mm2, and the number of layers are optimized at 10. Elaborating more on LPDDR4x analysis, PWL currents specific to each IO power supply bump are estimated based on worst-case switching activity. These PWL currents are then fed to the power supply bumps and IO noise is generated based on PDN in package and board. On-die decaps in the range of 6nF and package/board discrete decaps of values 0.1 μF, 1 μF and 10 μF are used to keep target impedance in the acceptable range. Jitter is estimated from worst-case peak to peak noise, which is called power supply-induced jitter (PSIJ). Deriving PSIJ separately for slow, typical and fast corners would reduce the pessimism involved in using the worst-case PSIJ for all the corners. After getting power supply-induced jitter, signal integrity simulation on the complete system chip+package+board is performed to evaluate write and read margins against the JEDEC eye mask. All the LPDDR4x routing in the package and PCB is done as stripline single-ended 40 Ω geometry and 70 Ω for DDR differentials (CLK and DQS) and maintained 2x spacing to have less crosstalks among the different DQ bits. NEXT and FEXT among DQ bits have been optimized to achieve a best return path scenario. To optimize return path, signal to ground ratio of the bump is kept at 2:1, and the ball has 1:1. Placing the ground ball ring at the PCB helps to improve return path and hence crosstalk. Locating DQS toward the center of the DQ byte group helps reduce DQ-to-DQ crosstalk. Ground via near the signal via improves the return path, and this guideline has been followed throughout the design. SI-PI co-simulation is performed by including the PSIJ into system write and read test benches. This approach eliminates any

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